Phase splitter circuit

ABSTRACT

A pair of output signals of equal magnitude and opposite phase are developed in response to the application of a single input signal. The output signals ride upon an output bias voltage which may be made to equal approximately one-half of an applied supply voltage.

United States Patent Schertz [451 Aug. 26, 1975 PHASE SPLITTER CIRCUIT [75] Inventor: Burtron D. Schertz, Kokomo, Ind.

[73]- Assignee: General Motors Corporation,

Detroit, Mich.

[22] Filed: July 11, 1974 211 App]. No.: 487,774

[52] US. Cl 307/262; 328/55 [51] Int. Cl. H03H 7/18 [58] Field of Search 307/262; 328/55 [56] References Cited OTHER PUBLICATIONS Phase Splitter, K. l-lelwig et al., IBM Tech. Disc. Bull.,

Vol. 12, No. ll, Apr. 1970.

Primary Examiner-John Kominski Attorney, Agent, or Firm-T. G. Jagodzinski [57] ABSTRACT A pair of output signals of equal magnitude and opposite phase are developed in response to the application of a single input signal. The output signals ride upon an output bias Voltage which may be made to equal approximately one-half of an applied supply voltage.

ZClaims, 1 Drawing Figure PATENTED AUG 2 6 I975 PHASE SPLITTER CIRCUIT This invention relates to a phase splitter circuit which is responsive to the application of an input signal to develop a pair of output signals of equal magnitude and opposite phase.

Ordinarily, the output signals of a phase splitter circuit are applied to drive a class B push-pull amplifier circuit or the like. In order to maximize the linear voltage swing of the driven circuit, it is desirable that the output signals of the phase splitter circuit ride upon an output bias voltage which is approximately equal to one-half of the applied supply voltage. The present invention provides a simple phase splitter circuit which is capable of achieving this desired result and which is suitable for fabrication as an integrated circuit or as a descrete circuit.

According to the invention, a phase splitter circuit includes identical left and right phase splitter networks as follows: A first transistor includes a base electrode connected to an input node, an emitter electrode connected to a feedback node, and a collector electrode connected to a load node. A second transistor includes a base electrode connected to the load node, an emitter electrode connected to an output node, and a collector electrode connected to a supply node. a third transistor includes a base electrode connected to a bias node, a collector electrode connected to the feedback node, and an emitter electrode. A first resistor is connected between the supply node and the load node. A second resistor is connected between the output node and the bias node. A third resistor is connected between the emitter electrode of the third transistor and a reference node. The series combination of a diode and a fourth resistor is connected between the bias node and the reference node. A fifth resistor is connected between the feedback nodes of the left and right networks.

As a result, in response to the application of an input signal E,- between one of the left and right input nodes and the reference node when a suitable input bias voltage V,, is applied between each of the input nodes and the reference node. left and right output signals E and E are developed between corresponding ones of the left and right output nodes and the reference node such that the left and right output signals E and E ride upon an output bias voltage V which is approximately defined by the following equation:

:i' R2 2 R :l 3 R3 R R, 1

5;] l [R2 R, 1 R,,

and such that the gain E /E,- and E,,,./E of the phase splitter circuit is approximately defined by the following equation:

values of the first, second, third, fourth and fifth resistors, respectively.

Provided that the following criteria are satisfied:

the output bias voltage V, is approximately defined by the following simplified equation:

s/2 which indicates that the output bias voltage 1 is equal to one-half of the supply voltage V Each of the above three criteria may be readily met whether the phase splitter circuit is fabricated as an integrated circuit or as a descrete, circuit.

These andother aspects and advantages of the invention may be best understood by reference to the following detailedjdescription of a preferred embodiment when taken in conjunction with the accompanying drawing.

In the drawing, the sole FIGURE is a schematic diagram of a phase splitter circuit incorporating the principles of the invention.

Referring to the drawing, a phase splitter circuit 10 includes a supply node 12 and a grounded reference node 14 across which a supply voltage V is applied. The phase splitter circuit 10 includes identical left and right phase splitter networks 16, and 16,.

In the left phase splitter network 16,, a first transistor 18, includes a base electrode connected directly to an input node 20,, a collector electrode connected directly to a load node 22,, and an emitter electrode connected directly to a feedback node 24,. A second transistor 26, includes a base electrode connected directly to the load node 22,, a collector electrode connected directly to the supply node 12, and an emitter electrode connected directly to an output node 28,. A third transistor 30, includes a base electrode connected directly to a bias node 32, and a collector electrode connected directly to the feedback node 24,. The transistor 30, also includes an emitter electrode. A fourth transistor 34, includes a base electrode and a collector electrode both connected directly to the bias node 32,. The transistor 34, also includes an emitter electrode.

Further, in the left phase splitter network 16,, a first resistor 36, is connected between the supply node 12 and the load node 22,. A second resistor 38, is connected between the output node 28, and the bias node 32,. A third resistor 40, is connected between the emitter electrode "of the third transistor 30, and the reference node 14. A fourth resistor 42, is connected between the emitter electrode of the fourth transistor 34, and the reference node 14.

Since the right phase splitter network 16, is identical to the left phase splitter network 16,, like numerals are used to denote like elements except that the numberals designating elements in the right phase splitter network 16,. have subscripts r while the numerals designating elements in the left phase splitter network 16, have subscripts f. In addition, a fifth resistor 44 is connected between the feedback node 24,in the left network 16, and the feedback node 24, in the right network 16,.

It will'bc noted that the left and right fourth transistors 34, and 34, are actually connected to function as diodes. In effect, the diode-connected transistors 34, and 34, have an anode electrode connected directly to a corresponding one of the left and right bias nodes 32, and 32, and a cathode electrode connected to a corresponding one of the left and right fourth resistors 42, and 42,. Thus, where the illustrated phase splitter circuit is to be fabricated as a descrete circuit, the devices 34, and 34,. would be provided by ordinary diodes. However, for reasons which will be more fully explained later, the illustrated phase splitter circuit 10 is preferably fabricated as an integrated circuit. Accordingly, the devices 34, and 34, are depicted in the drawing in the transistorized form" which has become conventional for the illustration of an integrated circuit diode.

A voltage divider network 46 is provided for applying a suitable input bias voltage V to the phase splitter circuit 10. The voltage divider network 46 comprises a first leg connected between the supply node 12 and a voltage divider node 48 and a second leg connected between the voltage divider node 48 and the reference node 14. The first voltage divider leg includes resistor 50, the base-emitter junction of transistor 52, and the base-emitter junction of transistor 54. The second voltage divider leg includes resistor 46 and the parallel connection of the base-emitter junction of transistor 58 and the base-emitter junction of the diode-connected transistor 60.

Preferably, the resistance of the resistor 50 is approximately twice the resistance of the resistor 56 so that the input bias voltage V defined between the voltage divider node 48 and the reference node 14 is about one-third of the supply voltage V, applied between the supply node 12 and the reference node 14. A pair of resistors 62 and 64 apply the input bias voltage V from the voltage divider node 48 to the left and right input nodes 20, and 20, of the phase splitter circuit 10, respectively. It is to be understood that the precise form of the voltage divider network 46 is not of critical importance. Accordingly, the illustrated voltage divider network 46 may be replaced by virtually any network capable of generating the desired input bias voltage V,,

Assuming that an input signal E,- having an increasing amplitude is applied between the left input node 20, and the reference node 14 on top of the input bias voltage V,, the conduction of current through the left first transistor 18, and the left first resistor 36, increases thereby lowering the potential at the left load node 22,. As the potential at the load node 22, decreases, the conduction of current through the left second transistor 26, decreases thereby decreasing the amplitude of the left output signal E defined between the left output node 28, and the reference node 14. Thus, the left output signal E is out of phase with the input signal E5.

The decrease in the potential at the left output node 28, is coupled through the left second resistor 38, to lower the potential at the left bias node 32,. As the potential at the bias node 32, decreases, the conduction of current through the left diode 34, and the left fourth resistor 42, decreases thereby equally decreasing the conduction of current through the left third transistor 30, and the left third resistor 40,. With the conduction of current through the transistor 18, increasing and the conduction of current through the transistor 30, decreasing, the potential at the left feedback node 24, rises to force a feedback current through the resistor 44 thereby raising the potential of the right feedback node As the potential at the right feedback node 24,- increases, the conduction of current through the right first transistor 18,- and the right first resistor 36,- decreases thereby raising the potential at the right load node 22,. As the potential at the load node 22, increases, the conduction of current through the right second transistor 26,. increases thereby increasing the amplitude of the right output signal E defined between the right output node 28,- and the reference node 14. Hence, the right output signal E is in phase with the input signal E,-.

The increase in the potential at the right output node 28,. is coupled through the right second reisistor 38, to raise the potential at the right bias node 32,. As the potential at the bias node 32, increases, the conduction of current through the right diode 34, and the right fourth resistor 42, increases thereby equally increasing the conduction of current through the right third transistor 30, and the right third resistor 40,-. With the conduction of current through the transistor 18, decreasing and the conduction of current through the transistor 30, decreasing, the potential at the right feedback node 24, is lowered to further increase the feedback current through the fifth resistor 44.

Through the foregoing analysis, it has been demonstrated that the application of an input signal E, between the left input node 20, and the reference node 14 results in the production of a left output signal E, from between the left output node 28, and the reference node 14 which is out of phase with the input signal E,- and results in the production of a right output signal E from between the right output node 28, and the reference node 14 which is in phase with the input signal E,-. By a similar analysis, it may be demonstrated that the application of an input signal E,- between the right input node 20, and the reference node 14 results in the production of a right output signal E,,, from between the right output node 28, and the reference node 14 which is out of phase with the input signal E,- and results in the production of a left output signal E from between the left output node 28, and the reference node 14 which is in phase with the input signal E,

In either of the above events, it can be additionally demonstrated that the right and left output signals E and E ride upon an output bias voltage V which is approximately defined by the following equation:

and that the gain E,,,/E,- and E,,,/E, is generally defined by the following equation:

left and right first resistors 36, and 36,, R is the resistance of the left and right second resistors 38, and 38,, R is the resistance of the left and right third resistors 40, and 40,. R, is the resistance of the left and right fourth resistors 42, and 42,, and R is the resistance of the fifth resistor '44.

Where the following three criteria are satisfied:

b. R R R,

c. R R, equation (1) is simplified to the following equation:

which indicates that the ouput'bias voltage V is equal to onehalf of the supply voltage V As previously pointed out, this is desirable where the left and right output signals E and E are to be applied to drive a Class B push-pull amplifier or the like. While each of the criteria (a), (b) and (c) can be met regardless whether the phase splitter circuit is fabricated as an integrated circuit or as a deserete circuit, they are more readily satisfied when the circuit 10 is integrated.

The correctness of equation (3) may be quickly verified by analyzing the phase splitter circuit 10 with respect to bias voltages and currents only. Referring particularly to the left phase splitter network 16,, it may be viewed as a voltage divider network having a first leg connected between the supply node 12 and the left output node 28, and having a second leg connected between the left output node 28, and the reference node 14. Equation (3) is correct if the voltage drop across the first voltage divider leg between the supply node 12 and the left output node 28,is equal to the voltage drop across the second voltage divider leg between the left output node 28, and the reference node 14.

The first voltage divider leg includes the first resistor 36, and the base-emitter junction of the second transistor 26,. The second voltage divider leg includes a first branch connected between the left output node 28, and the left bias node 32, and a second branch connected between the left bias node 32, and the reference node 14. The first branch includes the second resistor 38, only. The second branch includes parallel paths provided by the base-emitter junction of the third transistor 30, and the third resistor 40, and provided by the anode-cathode junction of the diode 34, and the fourth resistor 42,.

Assuming that the criterion (a) is satisfied so that the base-emitter junction voltage drop V of the third transistor 30, equals the anode-cathode junction voltage drop V, of the diode 34,, the current through the third and fourth resistors 40, and 42, is equal. Moreover, the current through the first resistor 36, is equal to the current through the third resistor 40, while the current through the second resistor 38, is equal to the current through the fourth resistor 42,. Consequently, the current through each of the resistors 36,, 38,, 40,, and 42, is identical.

Assuming that the criterion (0) is satisfied, the resistance R of the third resistor 40, is equal to the resistance R of the fourth resistor 42,. Since the current through the third and fourth resistors 40, and 42, is equal, the voltage drop across the third resistor 40, is equal to the voltage drop across the fourth resistor 42,. As a result, the third transistor 30,and the third resistor 40, may be disregarded in computing the voltage drop across the second branch of the first voltage divider leg which is equal to the summation of the voltage drop V,

across the anode-cathode junction of the diode 34, and the voltage drop across the fourth resistor 42,.

Assuming that the criterion (b) is satisfied, the resistance R of the first resistor 36, is equal to the summation of the resistance R of the second resistor 38, and the resistance R, of the fourth resistor 42,. Since the current through the first, second and fourth resistors 36,, 38, and 42, is equal, the voltage drop across the first resistor 36, is equal to the summation of the voltage drop across the second resistor 38, and the voltage drop across the fourth resistor 42,.

The voltage drop across the first voltage divider leg betweem the supply node 12 and the left output node 28, is equal to the summation of the voltage drop across the first resistor 36, and the base-emitter junction voltage drop V of the second transistor 26,. The voltage drop across the second voltage divider leg between the left output node 28, and the reference node 14 is equal to the summation of the voltage drop across the second resistor 38,, the anode-cathode junction voltage drop V, of the diode 34,, and the voltage drop across the fourth resistor 42,.

Due to the satisfaction of the criterion (a), the voltage drop V across the base-emitter junction of the second transistor 26, in the first voltage divider leg is equal to the voltage drop V, across the anode-cathode junction of the diode 34, in the second voltage divider leg. Further, due to the satisfaction of the criterion (b), the voltage drop across the first resistor 36, is equal to the summation of the voltage drop across the second resistor 38, and the voltage drop across the fourth resis tor 42,. Accordingly, the voltage drop across the first voltage divider leg between the supply node 12 and the left output node 28, is equal to the voltage drop across the second voltage divider leg between the left output node 28, and the reference 14. Thus, the validity of equation (3) is verified. A similar analysis may be made for the right phase splitter network 16,.

It will now be appreciated that the illustrated embodiment of the inventive phase splitter circuit 10 is shown for demonstrative purposes only and that various alterations and modifications may be made to this preferred embodiment without departing from the spirit and scope of the invention.

What is claimed is:

l. A phase splitter circuit for developing left and right output signals E and E of equal magnitude and opposite phase between corresponding ones of left and right output nodes and a reference node in response to the application of a single input signal E,- between one of left and right input nodes and the reference node when a supply voltate V,- is applied between a supply node and the reference node and when a suitable input bias voltage V is applied between each of the left and right input nodes and the reference node, comprising: left and right first transistors each having a base electrode connected to a corresponding one of left and right input nodes, each having an emitter electrode connected to a corresponding one of left and right feedback nodes and each having a collector electrode connected to a corresponding one of left and right load nodes; left and right second transistors each having a base electrode connected to a corresponding one of the left and right load nodes, each having an emitter electrode connected to a corresponding one of left and right output nodes, each having a collector electrode connected to a single supply node, and each exhibiting a characteristic base-emitter junction voltage V left and right third transistors each having a base electrode connected to a corresponding one of left and right bias nodes, each having a collector electrode connected to a corresponding one of the left and right feedback nodes, each having an emitter electrode, and each exhibiting a characteristic baseemitter junction voltage V left and right fourth transistors each having a base electrode connected to a corresponding one of the left and right bias nodes, each having a collector electrode connected to a corresponding one of the left and right bias nodes, each having an emitter electrode, and each exhibiting a characteristic base-emitter junction voltage V left and right first resistors each exhibiting a resistance R and each connected between a corresponding one of the left and right load nodes and the supply node; left and right second resistors each exhibitin g a resistance R and each connected between a corresponding one of the left and right output nodes and a corresponding one of the left and right bias nodes; left and right third resistors each exhibiting a resistance R;; and each connected between the emitter electrode of a corresponding one of the left and right third transistors and the reference node; left and right fourth resistors each exhibiting a resistance R and each connected between the emitter electrode of a corresponding one of the left and right fourth transistors and the reference node; and a fifth resistor connected between the left and right feedback nodes; whereby the left and righ output signals E and E ride upon an output bias voltage V1 hich is equal to one-half of the supply voltage V,, when the following criteria are satisfied:

2. ln combination: left and right first transistors each having base and emitter and collector electrodes, the base electrodes each connected to a corresponding one of left and right input nodes, the emitter electrodes each connected to a corresponding one of left and right feedback nodes, and the collector electrodes each connectcd to a corresponding one of left and right load nodes; left and right second transistors each having base and emitter and collector electrodes and each exhibiting a characteristic base-emitter junction voltage V the base electrodes each connected to a corresponding one of the left and right load nodes, the emitter electrodes each connected to a corresponding one of left and right output nodes, and the collector electrodes each connected to a single supply node; left and right third transistors each having base and emitter and collector electrodes and each exhibiting a characteristic base-emitter junction voltage V is the base electrodes each connected to a corresponding one of left and right diodes and the other of either the corresponding one of the left and right bias nodes or the reference node; and a fifth reisistor connected between the left and right feedback nodes whereby left and right output signals E and E of equal amplitude and opposite phase are developed between corresponding ones of the left and right output nodes and the reference node in response to the application of an input signal E,- between one of the left and right input nodes and the reference node when a supply voltage V is applied between the supply node and reference node and when a suitable input bias voltage V, is applied between the left and right output nodes and the reference node such that the left and right output signals E and E ride upon an output bias voltage V defined by the following equation:

and such that the voltage gain E /E and E /E,- is defined by the following equation: 

1. A phase splitter circuit for developing left and right output signals Eo and Eo of equal magnitude and opposite phase between corresponding ones of left and right output nodes and a reference node in response to the application of a single input signal Ei between one of left and right input nodes and the reference node when a supply voltate Vs is applied between a supply node and the reference node and when a suitable input bias voltage Vb is applied between each of the left and right input nodes and the reference node, comprising: left and right first transistors each having a base electrode connected to a corresponding one of left and right input nodes, each having an emitter electrode connected to a corresponding one of left and right feedback nodes and each having a collector electrode connected to a corresponding one of left and right load nodes; left and right second transistors each having a base electrode connected to a corresponding one of the left and right load nodes, each having an emitter electrode connected to a corresponding one of left and right output nodes, each having a collector electrode connected to a single supPly node, and each exhibiting a characteristic base-emitter junction voltage Vj ; left and right third transistors each having a base electrode connected to a corresponding one of left and right bias nodes, each having a collector electrode connected to a corresponding one of the left and right feedback nodes, each having an emitter electrode, and each exhibiting a characteristic base-emitter junction voltage Vj ; left and right fourth transistors each having a base electrode connected to a corresponding one of the left and right bias nodes, each having a collector electrode connected to a corresponding one of the left and right bias nodes, each having an emitter electrode, and each exhibiting a characteristic base-emitter junction voltage Vj ; left and right first resistors each exhibiting a resistance R1 and each connected between a corresponding one of the left and right load nodes and the supply node; left and right second resistors each exhibiting a resistance R2 and each connected between a corresponding one of the left and right output nodes and a corresponding one of the left and right bias nodes; left and right third resistors each exhibiting a resistance R3 and each connected between the emitter electrode of a corresponding one of the left and right third transistors and the reference node; left and right fourth resistors each exhibiting a resistance R4 and each connected between the emitter electrode of a corresponding one of the left and right fourth transistors and the reference node; and a fifth resistor connected between the left and right feedback nodes; whereby the left and righ output signals Eo and Eo ride upon an output bias voltage Vb which is equal to one-half of the supply voltage Vs when the following criteria are satisfied: Vj Vj Vj R1 R2 + R4 R3 R4.
 2. In combination: left and right first transistors each having base and emitter and collector electrodes, the base electrodes each connected to a corresponding one of left and right input nodes, the emitter electrodes each connected to a corresponding one of left and right feedback nodes, and the collector electrodes each connected to a corresponding one of left and right load nodes; left and right second transistors each having base and emitter and collector electrodes and each exhibiting a characteristic base-emitter junction voltage Vj , the base electrodes each connected to a corresponding one of the left and right load nodes, the emitter electrodes each connected to a corresponding one of left and right output nodes, and the collector electrodes each connected to a single supply node; left and right third transistors each having base and emitter and collector electrodes and each exhibiting a characteristic base-emitter junction voltage Vj , the base electrodes each connected to a corresponding one of left and right diodes and the other of either the corresponding one of the left and right bias nodes or the reference node; and a fifth reisistor connected between the left and right feedback nodes whereby left and right output signals Eo and Eo of equal amplitude and opposite phase are developed between corresponding ones of the left and right output nodes and the reference node in response to the application of an input signal Ei between one of the left and right input nodes and the reference node when a supply voltage Vs is applied between the supply node and reference node and when a suitable input bias voltage Vb is applied between the left and right output nodes and the reference node such that the left and right output signals Eo and Eo ride upon an output bias voltage Vb defined by the following equation: 